The ongoing scaling of transistors presents an ever expanding array of new issues to be overcome as the transistor dimensions shrink. Once such issue concerns a protection of the transistor gate from shorting with respect to the transistor contacts.
Gate protection according to the prior art may be achieved using a gate recess followed by a silicon nitride fill and planarization. Referring for example to FIGS. 1a and 1b, a prior art transistor fabrication contemplating gate protection typically involves a recessing of the transistor gates followed by a silicon nitride fill. Thus, as seen in FIG. 1a, a transitional transistor structure 100 has been provided with recessed gates 102 including recesses 104 defined between spacers 105. By “transitional gate structure,” what is meant in the context of the instant description if a transistor structure including a transistor gate where a fabrication of the transistor device has not yet come to completion. In the case of the shown structure of FIGS. 1a and 1b, contact regions for example have not yet been provided. The structure 100 further includes, as would be readily recognizable by the skilled person, a buried oxide layer 106 and an ILD oxide layer 108 on the buried oxide layer. A diffusion layer 110 supports the transistor gates and the spacers thereon. The diffusion layer 110, gates 102 and spacers 105 form transistor structure 112. the gate recess etch may be done with a selective etch. For example, aluminum gates could be etched using a chlorine dry etch without attacking the silicon oxide of ILD oxide layer 108. If the gate metals are different, then a different dry etch can be used or a combination of dry and wet etch can be used, especially to remove metals completely in the recess regions 104. Referring next to FIG. 1b, the deposition of silicon nitride (SiN) in recess regions 104 forms caps 114 over gates 102. After SiN deposition, a self aligned contact etch followed by contact metal deposition and planarization may be formed to form self aligned contact areas in a well known manner. Thereafter, a layer of contact metal may be deposited onto the self aligned contact areas, and planarized by being polished or etched to form contact regions. The prior art additionally discloses provided a metal one layer directly onto the diffusion layer without the use of self-aligned contact regions.
Disadvantageously, as gate lengths are scaled down, gate protection through the provision of capped gate recess regions has sometimes presented challenges, at least in view of the difficulty in controlling the gate's vertical dimension. A recessing of the gate and a planarization of the SiN cap reduces gate height in the prior art, resulting among other things in diminishing process margins.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.